Returning to his senior year of high school, he went all in and made billions by buying at the botto

After the Spring Festival, Qingjia did not have to wait long.

Early morning of February 22nd.

The first batch of wafers that have been manufactured has officially rolled off the production line.

The temperature-controlled, shockproof box containing the wafers was transported out of the factory by a special vehicle, escorted by two engineers from Tsinghua University and confidential personnel dispatched by the National Integrated Circuit Industry Investment Fund.

When the vehicle arrived in Kyoto, the Qingjia Laboratory Building had been closed for a full six hours.

All personnel involved in wafer screening, dicing, and packaging were re-identified, and their mobile phones, watches, and personal computers were all left in external safes.

Chen Mo returned to Kyoto from Jiangcheng that same day.

When he pushed open the door to the underground heavily anti-static zone, Wu Huaqiang was standing in front of the automated wafer probe station, surrounded by a large group of process and testing experts.

On the high-magnification optical scanning screen, countless uncut wafers lit up one by one like a star array.

Green indicates approval.

Red indicates that the code is invalid.

During the initial lighting of the dozen or so core particles, the spacious cleanroom was so quiet that even breathing could not be heard.

Only after the entire 12-inch wafer completed its first round of wafer-level initial testing and the robotic arm slowly returned to its position did Wu Huaqiang abruptly remove his dustproof goggles, his knuckles turning white as he rubbed his temples.

"The core yield is calculated to be 88.7%."

"Control core, 93.2%"

"Cache and in-memory computing integrated chips, all exceeding 9."

These figures are not particularly impressive for mature technologies.

But for a brand-new team that was running a complete heterogeneous system for the first time and working with local contract manufacturers on underlying processes for the first time, this was almost a miracle.

More importantly, the heterogeneous approach of breaking down a massive single chip into micro-chips demonstrates unparalleled fault tolerance advantages at this moment.

Localized wafer defects will only destroy one or two tiny chips, without scrapping the entire high-cost wafer.

Gu Shaoting stood at the back of the crowd, his eyes cold and stern, without a trace of a smile.

"The fact that a wafer can pass the test only proves that each building block is usable individually."

The old man looked at the wafer on the probe table.

Whether they can actually be put together depends on the packaging.

After two days of screening, Ching Chip selected four groups of known good chips from the first batch of wafers.

The computation, control, caching, and storage are each divided into separate components.

They are fed into a pre-reserved high-density packaging line, placed on the interposer layer according to the final drawings, and then assembled into a complete system through micro-bumps and high-density interconnects.

February 27th, 11:40 PM.

The first engineering sample has been packaged and tested.

The silver-gray package was fixed to the center of the test motherboard.

After verifying all power supplies, measuring probes, and external interfaces, Wu Huaqiang personally pressed the start button.

The indicator lights on the test bench lit up one by one.

Power supply is normal.

Control chip startup.

Four cache groups were identified.

The calculation core returns the first status message.

The suppressed breathing that had been building up in the lab finally eased.

Just as someone was about to applaud, a yellow warning suddenly popped up in the lower right corner of the screen.

A verification error occurred in the third storage channel.

It started only once.

Subsequently, the number of errors began to increase rapidly.

In the thirteenth minute, the third and fourth storage channels were simultaneously interrupted.

In the twenty-first minute, the dispatch system became unresponsive.

The entire test motherboard automatically shut down.

The initial joy vanished quickly.

The technicians immediately replaced the sample with a second one.

The results were almost identical.

It operates normally under low load.

As the temperature rose, errors began to occur in the external storage channels, eventually causing the entire system to crash.

The third sample only lasted nine minutes.

Three o'clock in the morning.

Qingjia held an emergency fault analysis meeting.

The clock, power supply, scheduling, interface, and packaging teams were all present.

Some suspect that there is a fundamental flaw in the clock synchronization between multiple chips.

Some argue that crosstalk occurs in long-distance wiring of the interposer layer at high frequencies, and existing compensation algorithms are simply unable to maintain signal integrity.

If either of these two judgments is true, Qingjia will have to revise the map again.

The second round of tape-out will take at least two more months.

An even more serious consequence is that the entire heterogeneous architecture proposed by Chen Mo needs to be re-evaluated.

The atmosphere in the meeting room grew increasingly heavy.

Gu Shaoting remained silent throughout.

He had each group project all the raw data onto the screen and eliminate possibilities one by one.

Chen Mo also didn't rush to speak.

He knew this route could succeed, but he didn't know where the problem lay.

During the hour and a half of noisy deliberations, Chen Jing, who had been sitting at the very end of the long table, suddenly stood up.

"Replace the channel number with the physical location."

The engineer operating the computer didn't understand.

"What do you mean?"

"Do not arrange according to logical numbering."

Chen Jing walked to the screen.

"Mark the actual location of the chip within the package for each error channel."

The engineer quickly retrieved the packaging diagram.

The third and fourth groups, as well as the two backup channels where the second sample had a problem, were marked in red in turn.

All the red dots are concentrated at the outer edge of the intermediate layer.

The meeting room gradually quieted down.

Chen Jing then had someone overlap the temperature curve with the incorrect time.

When the first batch of errors occurred, the core temperatures of the several samples were not the same.

The temperature difference at the edges of the package is almost uniform.

"If it's a clock or scheduling logic, the error should follow changes in channel functionality and workload."

Chen Jing pointed at the screen.

"The problem now is always with external interconnectivity."

"And it always happens after the second round of warming."

"I suspect that there is localized warping in the package."

The packaging team leader immediately stated, "No cracks were found during room temperature scanning, and the flatness is within the process standards."

"Then don't just measure the room temperature."

Chen Jing looked at him.

"After the sample cools down, the microbumps may re-engage. Only when the temperature rises and the material's coefficient of thermal expansion changes will the outer edges be pulled apart."

"Perform on-load thermal imaging and dynamic impedance testing."

"Take another sample and perform destructive sectioning."

The person in charge of packaging hesitated for a moment.

The first batch of complete sample pieces consisted of only four pieces.

Three have already been used for testing.

If another piece is cut open, Qingjia will temporarily have no complete slices left.

"cut."

Gu Shaoting made a decision.

"We can't bear to part with a single sample now, because the entire batch of wafers will be scrapped later."

The failure analysis team was activated overnight.

The fourth sample was ground, polished, and sliced ​​layer by layer.

9:40 a.m.

High-magnification micrographs appear on the screen.

Around the rows of micro-bumps on the outer side of the interlayer, there are tiny cracks that are not visible to the naked eye.

The crack can remain in contact at room temperature.

After being heated and energized, the contact resistance increases rapidly, eventually causing the signal to be interrupted.

The architecture did not fail.

The problem lies in the packaging process.

The packaging plant replaced a batch of bottom filler materials during the Spring Festival.

The curing temperature of the new material differs from that of the European test samples, but the production line uses the original heating curve.

A rapid heating process creates additional stress in the interlayer, substrate, and filler material after cooling.

The warpage compensation parameters that Chen Jing had previously established were correct.

The actual packaging conditions have changed.

She wrote the new material parameters into the model and then worked with the packaging team to break down the curing process again.

The rapid, single-stage heating process has been changed to segmented pre-curing.

Temporary support structures were added to the outer edge.

The pressing, cooling, and stress release times have all been readjusted.

The backup packaging line was prepared starting at noon that day.

The remaining known good chips were urgently sent to a second packaging and testing company.

Wen Zhixia was responsible for all coordination between the two locations.

She instructed the second packaging and testing company to suspend its original batch of projects, freeing up a packaging window for Qingjia, and completed the confirmation of new materials, the signing of confidential documents, and the change of transportation routes on the same day.

The handover, which originally took a week to complete, was compressed to within 72 hours.

Three days later.

Two repackaged engineering samples were returned to Qingjia.

……